1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device monolithically implementing a high-speed and high-frequency three-terminal switching device by connecting a bipolar power transistor and a power MOS-FET (metal-oxide semiconductor field-effect transistor) in parallel with each other.
2. Description of the Prior Art
Bi-MOS devices (combinations of bipolar power transistors and power MOS-FETs) of various circuit configurations are generally employed as high-speed and high-frequency switching devices. Description is now made of some of the circuit configurations of the conventional Bi-MOS devices.
FIG. 1 shows a circuit configuration of a conventional switching device which consists of a Darlington-connected Bi-MOS device. With reference to FIG. 1, the circuit configuration of the conventional device is now described.
An n-channel power MOS-FET 2 and an npn bipolar power transistor 3 are Darlington-connected with each other. Namely, the drain of the MOS-FET 2 is connected with the collector of the bipolar transistor 3 while the source of the MOS-FET 2 is connected with the base of the bipolar transistor 3. A shunt resistor 4 is interposed between the base and the emitter of the bipolar transistor 3 while a freewheeling diode 5 is provided between the emitter and the collector of the bipolar transistor 3 in an electrically forward direction in view of the emitter. A driver 1 supplies switching signals between the gate of the MOS-FET 2 and the emitter of the bipolar transistor 3. The driver 1 also supplies the signals between the gate of the MOS-FET 2 and one end of the shunt resistor 4.
FIG. 2 is a sectional view of the Bi-MOS device as shown in FIG. 1.
Referring to FIG. 2, the n-channel MOS-FET 2 is formed of an n.sup.+ -type semiconductor substrate 11 having relatively high-concentrated n-type impurities, an n.sup.- -type epitaxial semiconductor layer 12 formed on the n.sup.+ -type semiconductor substrate 11 and having relatively low-concentrated impurities, a p-type impurity-diffused region 13b formed in a predetermined region on the n.sup.- -type layer 12, an n.sup.+ -type impurity-diffused region 14b formed in the p-type region 13b and a gate electrode 17 formed in a predetermined region on the n.sup.- -type layer 12. An electrode interconnection 18b is provided commonly for the p-type region 13b and the n.sup.+ -type region 14b. The n.sup.+ -type substrate 11 is provided on its surface with a conductive film 10 which, in turn, serves as an electrode.
The n.sup.+ -type region 14b serves as a source region, while the n.sup.- -type layer 12 and the n.sup.+ -type substrate 11 serve as drains. An inversion layer (channel) is formed in a region of the p-type region 13b under the gate electrode 17.
The npn bipolar transistor 3 consists of a collector region formed of the n.sup.+ -type substrate 11 and the n.sup.- -type layer 12, a base region consisting of a p island region 13a formed in a prescribed region on the n.sup.- -type layer 12 and an emitter region consisting of an n.sup.+ -type region 14a formed in the p island region 13a. As obvious from FIG. 2, the drain region of the MOS-FET 2 and the collector region of the bipolar transistor 3 share the n.sup.- -type layer 12 and the n.sup.+ -type substrate 11.
Operation of the conventional device is now described with reference to FIGS. 1 and 2.
In turn-on operation, the driver 1 supplies a pulse of positive voltage (voltage in view of the gate of the MOS-FET 2; this also applies to the following description) between the gate 17 and the source 14b of the MOS-FET 2. When the positive voltage pulse exceeds threshold voltage between the gate and the source of the MOS-FET 2, the MOS-FET 2 is turned on whereby a current flows between the drain 11, 12 and the source 14b through the channel formed in the p-type region 13b. The current serves as the forward base current to the bipolar transistor 3 to cause saturation between the base and the emitter, whereby the bipolar transistor 3 is turned on.
In turn-off operation, the driver 1 supplies a negative voltage pulse (voltage in view of the gate of the MOS-FET 2; this also applies to the following description) between the gate and the source of the MOS-FET 2, whereby the MOS-FET 2 is turned off. In response to this, a reverse bias base current to the bipolar transistor 3 flows through the collector 11, 12, the base 13a and the shunt resistor 4, whereby the bipolar transistor 3 is turned off. The switching operation has been performed in the aforementioned manner.
In the above described three-terminal monolithic Darlington-connected Bi-MOS device, however, the MOS-FET 2 and the bipolar transistor 3 are in Darlington operation and hence effects of bipolar operation are remarkable, whereby the following problems are caused:
(a) The switching speed of the bipolar transistor 3 is only slightly higher than that of an ordinary bipolar transistor, resulting from the storage time thereof.
(b) The reverse bias safe operating area is substantially similar to that of the ordinary bipolar transistor.
(c) Secondary breakdown with respect to the area of safety operation is substantially identical to that of the ordinary bipolar transistor.
(d) The shunt resistor 4 is provided in order to flow the reverse bias current for turning off the bipolar transistor 3, and hence the base current at the time of turning-on is bypassed through the shunt resistor 4.
(e) In the monolithic configuration, reduction of the chip size is restricted since the MOS-FET and the bipolar transistor are formed in different regions on the same substrate as shown in FIG. 2.
FIG. 3 shows the circuit configuration of a conventional four-terminal cascode-connected Bi-MOS device for high-speed switching operation, which is formed in a hybrid manner. With reference to FIG. 3, description is now made on the circuit configuration and operation.
An n-channel MOS-FET 2 and an npn bipolar power transistor 3 are cascode-connected with each other. Namely, the drain of the MOS-FET 2 is connected with the emitter of the bipolar power transistor 3, while the source of the MOS-FET 2 is connected with the collector of the bipolar power transistor 3 through a freewheeling diode 5. Further, the source of the MOS-FET 2 is connected with the base of the bipolar power transistor 3 through a DC (direct current) voltage source 6. A driver 1 supplies switching signals between the gate and the source of the MOS-FET 2. The freewheeling diode 5 is electrically forwardly connected in view of the source of the MOS-FET 2. The DC voltage source 6 is so connected as to apply forward bias voltage between the base and the emitter of the bipolar transistor 3 and supply a necessary base current. Description is now made of operation of the device.
In turn-on operation, the driver 1 supplies a positive voltage pulse between the gate and the source of the MOS-FET 2. When the applied pulse voltage exceeds threshold voltage between the gate and the source of the MOS-FET 2, the MOS-FET 2 is turned on. In response to this, a current flows out from the DC voltage source 6 as a base current to the bipolar transistor 3, then flows between the base and the emitter of the bipolar transistor 3, and further flows between the drain and the source of the MOS-FET 2, whereby the bipolar transistor 3 is turned on.
In turn-off operation, the driver 1 supplies a negative voltage pulse to the gate of the MOS-FET 2, whereby the MOS-FET 2 is turned off. As a result, the output path of the emitter of the bipolar transistor 3 is cut off whereby the bipolar transistor 3 is turned off.
The three-terminal cascode-connected Bi-MOS switching device in the aforementioned structure has the following disadvantages:
(a) The voltage source is provided for applying forward bias voltage between the base and the emitter of the bipolar transistor 3 whereby the driver 1 and the voltage source 6 are both required as driving circuits, and hence the device is increased in size in comparison with an ordinary device. Further, the base current flows through the voltage source 6, whereby power loss is increased in driving the device.
(b) Voltage drops are caused in both of the MOS-FET 2 and the bipolar transistor 3, whereby the power loss in an ON state is increased in comparison with ordinary bipolar transistor and MOS-FET.
(c) It is considerably difficult to form the device in monolithic structure.
(d) The external size of the entire device is increased in a hybrid combination.
FIG. 4 shows the circuit configuration of a conventional four-terminal parallel-connected Bi-MOS device for high-speed switching in hybrid structure. With reference to FIG. 4, description is now made of the circuit configuration and operation of the four-terminal parallel Bi-MOS device.
An n-channel MOS-FET 2 and a bipolar power transistor 3 are connected in parallel with each other. Namely, the drain of the MOS-FET 2 is connected with the collector of the bipolar transistor 3, and the source of the MOS-FET 2 is connected with the emitter of the bipolar transistor 3. A freewheeling diode 5 is connected between the emitter and the collector of the bipolar transistor 3 (between the source and the drain of the MOS-FET 2) in an electrically forward direction in view of the emitter (source). A driver 1 supplies signals for switching operation between the gate and the source of the MOS-FET 2, while a base driving current source 7 supplies signals for driving the bipolar transistor 3 between the base and the emitter of the bipolar transistor 3. The operation of this device is now described.
The driver 1 supplies a positive voltage pulse to the gate of the MOS-FET 2, which in turn enters an ON state. In synchronization with the positive voltage signal from the driver 1, the base driving current source 7 supplies a current pulse to the base of the bipolar transistor 3. The bipolar transistor 3 enters an ON state in response to the current pulse, whereby the MOS-FET 2 and the bipolar transistor 3 perform parallel switching operation. However, the switching speed of the MOS-FET 2 is higher than that of the bipolar transistor 3, and hence a load current flowing from a C/D terminal (junction between the drain of the MOS-FET 2 and the collector of the bipolar transistor 3) is first bypassed by the MOS-FET 2, to flow out from an E/S terminal (junction between the source of the MOS-FET 2 and the emitter of the bipolar transistor 3). Then the bipolar transistor 3 is turned on responsive to saturation between the base and the emitter, whereby the current flowing from the C/D terminal to the E/S terminal is divided according to the ratio of the voltage drop between the collector and the emitter of the bipolar transistor 3 to that between the drain and the source of the MOS-FET 2.
In turn-off operation, the driver 1 supplies any positive voltage to the gate of the MOS-FET 2, while a negative current pulse is synchronously supplied to the base of the bipolar transistor 3. The current flowing between the collector and the base of the bipolar transistor 3 is extremely small in an ON state (because of non-saturation between the collector and the base), whereby the storage time is short and the device enters an OFF state at a high speed.
The four-terminal parallel-connected Bi-MOS device in the aforementioned discrete structure has the following disadvantages:
(a) The device requires two driving circuits, i.e., the driver 1 for driving the MOS-FET 2 and the base driving current source 7 for driving the bipolar transistor 3, whereby the driving circuit formed of the two driving circuits is increased in scale.
(b) It is necessary to supply the base current from the base driving current source 7 to the bipolar transistor 3, whereby electric power loss is increased in driving.
(c) It is considerably difficult to design the MOS-FET 2 and the bipolar transistor 3 to be synchronized in switching operation.
(d) Since the MOS-FET 2 and the bipolar transistor 3 are separately driven by the two driving circuits, a dV/dt phenomenon may be caused when they are not synchronized in switching operation.
(e) The device is in hybrid structure, whereby the external size thereof is increased.
FIG. 5 shows the circuit configuration of a conventional four-terminal synthesis Bi-MOS device for high-speed switching. With reference to FIG. 5, description is now made of the circuit configuration and the structure of the circuit.
In the circuit as shown in FIG. 5, an n-channel power MOS-FET 2 is Darlington-connected with a bipolar power transistor 3, while the bipolar transistor 3 is cascode-connected with a MOS-FET 9. Namely, the drain of the MOS-FET 2 is connected with the collector of the bipolar transistor 3, and the source thereof is connected to the base of the bipolar transistor 3. The emitter of the bipolar transistor 3 is connected with the drain of the MOS-FET 9, while the collector thereof is connected with the source of the MOS-FET 9 through a freewheeling diode 5. The freewheeling diode 5 is connected in an electrically forward direction in view of the source of the MOS-FET 9. A zener diode 8 is interposed between junction S.sub.1 of the source of the MOS-FET 2 and the base of the bipolar transistor 3 and the source of the MOS-FET 9 in an electrically reverse direction in view of the terminal S.sub.1. A driver 1 supplies switching signals to both of the gates of the MOS-FETs 2 and 9. Description is now made of operation of the illustrated circuit.
In turn-on operation, the driver 1 supplies a positive voltage pulse between the respective gates and sources of the MOS-FETs 2 and 9. In response to this, the MOS-FETs 2 and 9 are both turned on. A current flowing between the drain and the source of the MOS-FET 2 flows as a forward bias base current to the bipolar transistor 3 through the junction S.sub.1, whereby the bipolar transistor 3 is turned on. Breakdown voltage of the zener diode 8 is set to be larger than the total sum of saturation voltage between the base and the emitter of the bipolar transistor 3 and the voltage drop between the drain and the source of the MOS-FET 9, so that all of the base currents do not flow through the zener diode 8.
In turn-off operation, the driver 1 supplies a negative voltage pulse to the gates of the MOS-FETs 2 and 9. In response to this, the MOS-FETs 2 and 9 enter OFF states, whereby the output path of the emitter of the bipolar transistor 3 is cut off. In response to this, the collector current of the bipolar transistor 3 flows as a reverse bias current through the collector and the base to be bypassed through the zener diode 8, whereby the bipolar transistor 3 is turned off.
The synthesis Bi-MOS device in the aforementioned discrete structure has the following disadvantages:
(a) After the MOS-FET 9 is turned off and the emitter of the bipolar transistor 3 is cut off, the reverse bias current flows by way of the collector, the base and the zener diode 8 resulting from the stored charges in the bipolar transistor 3, whereby the reverse bias safe operating area is narrowed.
(b) The collector current flowing through the bipolar transistor 3 is bypassed through the zener diode 8 during the storage time in turn-off operation, and hence electric power loss is increased with increase in zener voltage of the zener diode 8.
With a conventional synthesis Bi-MOS device, the zener voltage of the zener diode 8 is set to be larger than the total voltage of the saturation voltage between the base and the emitter of the bipolar transistor 3 and the voltage drop between the drain and the source of the MOS-FET 9 so that the base current can not be bypassed through the zener diode 8 in turn-on operation. Thus, inevitably is the electric power loss is increased in the zener diode 8 during the storage time in turn-off operation.
(c) The feedback capacitance (capacitance between a gate and a drain) of the MOS-FETs 2 and 9 and the inductance of this circuit form an oscillation circuit, which may oscillate in turn-on operation to break the device.
(d) Electric power loss in the ON state of the device is increased by the total of the voltage drop across the MOS-FET 9 by ON resistance thereof and the saturation voltage drop across the bipolar transistor 3.
(e) MOS-FETs 2 and 9 and the bipolar transistor 3, are all required whereby the chip size is increased.
Further, this device is in the largest size within Bi-MOS devices in hybrid combinations.
Three types of Bi-MOS transistors (cascade, cascode and parallel combinations) are disclosed in "A Comparison Between Bi-MOS Device Types", M. S. Adler, IEEE Power Electronics Specialists Conference, June 1982, pp. 371-377.